december 1998 1/4 AN967 application note embedded application benefits from the m48t559 the m48t559 integrates, in a single package, several of the functions that an application designer rou- tinely needs. it contains both a 64 kbit (8k x 8) array of low power, non-volatile, static ram, and a real time clock. it also contains its own integrated crystal oscillator, and its own emergency battery supply (in the snaphat package). when external power is being supplied, the memory gives all the speed and access advantages of static ram; and the clock information, located in addresses 1ff8h-1fffh, are accessed in the same way as the normal locations in the memory array. when the external power is removed, the device switches to internal battery power, thereby giving the ad- vantages of non-volatile storage (for 7 years, or more). the internal battery also allows the clock to con- tinue operating, and the alarms to be monitored. for instance, the m48t559 can be programmed to power up the rest of the system even during battery backup. other hardware functions, such as microprocessor reset and interrupt functions, are also available. along with the power-fail detection circuitry, the m48t559 contains a programmable watchdog timer, which may be used to detect hung-bus conditions. the watchdog circuit, whose period can be set in the range 1/16 of a second to 124 seconds, can also be programmed to reset, or to interrupt, the microcon- troller. the provision of all this functionality, performed independently of the microcontroller, and in a single pack- age, not only minimises the chip count, but also frees the microcontroller for other computation, or to be shut down when it is not needed. economising on use of microcontroller ports another distinctive feature of the m48t559 is that it provides address/address/data multiplexing. this is another hardware reduction feature, and allows for a substantial saving in the port usage on the microcon- troller. most microcontrollers allow access to external memory devices, but they must tie up additional ports to obtain the high order address lines. the number of ports needed can be significantly reduced by address / address / data multiplexing. of course, address / data multiplexing has been used for a long time, but this only multiplexes the eight lower order address lines. figure 1 shows the implementation of this more traditional type of address / data multiplexing. the ea pin is tied appropriately for dedicating all of the bits in port 0 and port 2 for external memory access. an ex- ternal latch is also required to hold the lower order address information during the entire access cycle.
AN967 - application note 2/4 figure 1. address / data multiplexing ai02479 p3.7 ale p3.6 p2.4 p2.3 p2.2 p2.1 p2.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.1 p0.0 p0.2 74573 8k x 8 sram 8051 a7 a6 a5 a4 a3 a1 a0 a2 dq7 dq6 dq5 dq4 dq3 dq1 dq0 dq2 g w a12 a11 a9 a8 a10 8d 7d 6d 5d 4d 2d 1d 3d c 8q 7q 6q 5q 4q 2q 1q 3q qc ea
3/4 AN967 - application note by contrast, full address / address / data multiplexing requires a slightly different approach to accessing external memory. by adding an additional address strobe, the high order address lines can also be made to share the same ports as the lower order address and data lines. figure 2 shows how this can be achieved, very economically, using the m48t559. the ea pin is tied low. this allows port 0 and port 2 to act like standard i/o ports. all address and data information is passed through port 0. bits 0 and 1 of port 2 are used to strobe both the lower and higher order address lines into the m48t559. since the m48t559 already incorporates address latches, it is not necessary to provide an external latch. the result from this configuration saves ports p2.2 through p2.7 for other uses. it also eliminates an external latch, and greatly reduces the metal routing on the circuit board that would have been used for the high order address. figure 2. address / address / data multiplexing since program code requires conventional memory access, program code needs to be stored in internal memory. for most microcontrollers this is not a problem, with internal eprom or rom being used for this purpose. selecting one of the devices will free the system to operate as a vector based system. ai02480 p3.7 p3.6 p2.1 p2.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.1 p0.0 p0.2 m48t559 8051 dq7 dq6 dq5 dq4 dq3 dq1 dq0 dq2 g w as1 as0 ea
AN967 - application note 4/4 if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.nvram@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 1998 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com
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